CLKO1_SEL=CLKO1_SEL_0, CLKO1_DIV=CLKO1_DIV_0, CLK_OUT_SEL=CLK_OUT_SEL_0, CLKO2_EN=CLKO2_EN_0, CLKO2_DIV=CLKO2_DIV_0, CLKO1_EN=CLKO1_EN_0
CCM Clock Output Source Register
| CLKO1_SEL | Selection of the clock to be generated on CCM_CLKO1 0 (CLKO1_SEL_0): pll3_sw_clk (divided by 2) 1 (CLKO1_SEL_1): PLL2 (divided by 2) 2 (CLKO1_SEL_2): ENET PLL (divided by 2) 11 (CLKO1_SEL_11): core_clk_root 12 (CLKO1_SEL_12): ipg_clk_root 13 (CLKO1_SEL_13): perclk_root 15 (CLKO1_SEL_15): pll4_main_clk |
| CLKO1_DIV | Setting the divider of CCM_CLKO1 0 (CLKO1_DIV_0): divide by 1 1 (CLKO1_DIV_1): divide by 2 2 (CLKO1_DIV_2): divide by 3 3 (CLKO1_DIV_3): divide by 4 4 (CLKO1_DIV_4): divide by 5 5 (CLKO1_DIV_5): divide by 6 6 (CLKO1_DIV_6): divide by 7 7 (CLKO1_DIV_7): divide by 8 |
| CLKO1_EN | Enable of CCM_CLKO1 clock 0 (CLKO1_EN_0): CCM_CLKO1 disabled. 1 (CLKO1_EN_1): CCM_CLKO1 enabled. |
| CLK_OUT_SEL | CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks 0 (CLK_OUT_SEL_0): CCM_CLKO1 output drives CCM_CLKO1 clock 1 (CLK_OUT_SEL_1): CCM_CLKO1 output drives CCM_CLKO2 clock |
| CLKO2_SEL | Selection of the clock to be generated on CCM_CLKO2 6 (CLKO2_SEL_6): lpi2c_clk_root 14 (CLKO2_SEL_14): osc_clk 16 (CLKO2_SEL_16): lpspi_clk_root 18 (CLKO2_SEL_18): sai1_clk_root 20 (CLKO2_SEL_20): sai3_clk_root 22 (CLKO2_SEL_22): trace_clk_root 27 (CLKO2_SEL_27): flexspi_clk_root 28 (CLKO2_SEL_28): uart_clk_root 29 (CLKO2_SEL_29): spdif0_clk_root |
| CLKO2_DIV | Setting the divider of CCM_CLKO2 0 (CLKO2_DIV_0): divide by 1 1 (CLKO2_DIV_1): divide by 2 2 (CLKO2_DIV_2): divide by 3 3 (CLKO2_DIV_3): divide by 4 4 (CLKO2_DIV_4): divide by 5 5 (CLKO2_DIV_5): divide by 6 6 (CLKO2_DIV_6): divide by 7 7 (CLKO2_DIV_7): divide by 8 |
| CLKO2_EN | Enable of CCM_CLKO2 clock 0 (CLKO2_EN_0): CCM_CLKO2 disabled. 1 (CLKO2_EN_1): CCM_CLKO2 enabled. |